This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, some memory devices attempt to support large range level shifting to enable Dynamic Voltage Frequency Scaling (DVFS). Some of these memories may support dual voltage rails, e.g., one for a bitcell core circuitry (VDDCE) and another for periphery circuitry (VDDPE). VDDCE lowering may be limited by bitcell retention voltage and is typically held at higher voltages compared to VDDPE. On the other hand, VDDPE lowering may be limited by internal circuitry. Typically, lowering VDDPE may be small, and this minor voltage difference may potentially limit an overall power savings on the chip, as a whole. Thus, there exists a need to improve integrated circuitry to enable Dynamic Voltage Frequency Scaling (DVFS) in a more efficient manner.